Why Superconducting Quantum Chip Package?

  • EM noise shielding
  • Microwave signal fan-out
  • Securing and protecting the chip

Design Requirement for the package:

  • Modular & scalable
  • High level of integration
  • Low dissipation rate
  • High fidelity

Designing Principles

Engineering concerns:

  • Low dissipation rate
    • Material selection
    • Supression of coupling to vibration mode
      • Cavity mode
      • PCB chip mode
  • High fidelity
    • Signal integrity engineering
      • Impedance matching
      • Reducing crosstalk

Cavity Mode

Half-integer times base frequency.

PCB Mode

\[f_{PCB}\approx 10.4 \rm{GHz}, Q=55\]

Impedance Matching

\(Z=\sqrt{L/C}\approx 200\Omega \rightarrow\) 3-4 wirebonds to match standard impedance \(Z_0=50\Omega\)

Where

\[L\approx \frac{\mu_0l}{2\pi} \rm{arccosh}(2h/d)\] \[C\approx \frac{2\pi l \varepsilon_0}{\rm{arccosh(h/d)}}\]

Verifying impedance by Time-Domain Reflectometry (TDR), matching is optimized for 3 wires diameter \(d=50\mu m\).

Grouding wires for crosstalk supression

Saturation after 1 grounding wire.

3D Pogo-pin-based Wiring Package Design

Pogo-pin-based 3D wiring

Scalable Quantum Chip Design

  • \(3\times 3\) cell forming a scalable 2D array
  • 36 tunable transmon qubits
  • Through silicon via (TSV) for front and back surface

  • +2MHz ~ -40MHz tunable coupling strength
  • multiplexed readin and readout.

Supression of Chip Mode

With the added central pillar, the band becomes much flatter, and cut-off freqency greatly increased to above 30GHz.

Supression of crosstalk

Coaxial microwave cable, nearest neighbor crosstalk < -100dB.